/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
 * Copyright (C) 2016-2018, LomboTech Co.Ltd.
 * Author: lomboswer <lomboswer@lombotech.com>
 *
 * Lombo VISS-MIPI-CSI controller register definitions header
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License along
 */

/******************************************************************************
 * Controller clock and reset configuration
 *****************************************************************************/

#ifndef ___VISS_MIPI__CSI___H___
#define ___VISS_MIPI__CSI___H___


/**
 * MIPI_CSI enable
 */
u32 csp_mcsi_enable(void *base);

/**
 * MIPI_CSI disable
 */
u32 csp_mcsi_disable(void *base);
/**
 * MIPI_CSI status
 */
u32 csp_mcsi_status(void *base);

/******************************************************************************
 * interface configure
 *****************************************************************************/

/**
 * Select MIPI_CSI data path
 */
u32 csp_mcsi_data_path(void *base, u32 path);

/**
 * Select MIPI_CSI video width
 */
/* u32 csp_mcsi_video_width(u32 width); */

/**
 * Select YUV componet sequence
 */
u32 csp_mcsi_component_sequence(void *base, u32 seq);

/**
 * Select long packet parse
 */
u32 csp_mcsi_parse_long_pkg(void *base, u32 en);

/**
 * data identifier config
 * @dt: [5:0], Data type
 * @vc: [7:6], Virtual channel
 */
u32 csp_mcsi_data_identifier_config(void *base, u32 ch, u32 dt, u32 vc);

void csp_mcsi_ints_enable(void *base, u32 interrput);

void csp_mcsi_ints_disable(void *base, u32 interrput);

u32 csp_mcsi_ints_pending(void *base);

void csp_mcsi_ints_clear(void *base, u32 interrput);

void csp_mcsi_contrl_ints_enable(void *base, u32 interrput);

void csp_mcsi_contrl_ints_disable(void *base, u32 interrput);

u32 csp_mcsi_contrl_ints_pending(void *base);

void csp_mcsi_contrl_ints_clear(void *base, u32 interrput);

void csp_mcsi_reg0_ints_enable(void *base, u32 interrput);

void csp_mcsi_reg0_ints_disable(void *base, u32 interrput);

u32 csp_mcsi_reg0_ints_pending(void *base);

void csp_mcsi_reg0_ints_clear(void *base, u32 interrput);

void csp_mcsi_reg1_ints_enable(void *base, u32 interrput);

void csp_mcsi_reg1_ints_disable(void *base, u32 interrput);

u32 csp_mcsi_reg1_ints_pending(void *base);

void csp_mcsi_reg1_ints_clear(void *base, u32 interrput);

void csp_mcsi_cfg_fifo(void);

u32 csp_mcsi_chk_lbor(void);

u32 csp_mcsi_set_channel_size(void *base, u32 mipi_ch, u32 x, u32 y);


/**
 * Reset MIPI_CSI circuit
 */
u32 csp_mcsi_reset(void *base);

/**
 * Config MIPI DPHY active lanes
 */
u32 csp_mipi_dphy_active_lane(void *base, u32 lane);

/**
 * MIPI DPHY shutdown
 */
u32 csp_mipi_dphy_shutdown(void *base);

/**
 * MIPI DPHY power up
 */
u32 csp_mipi_dphy_power_up(void *base);

/**
 * MIPI DPHY reset active
 */
u32 csp_mipi_dphy_reset_active(void *base);

/**
 * MIPI DPHY reset in-active
 */
u32 csp_mipi_dphy_reset_inactive(void *base);

/**
 * MIPI DPHY controller reset active
 */
u32 csp_mipi_dphy_controller_reset_active(void *base);

/**
 * MIPI DPHY controller reset in-active
 */
u32 csp_mipi_dphy_controller_reset_inactive(void *base);

/**
 * MIPI DPHY status
 */
u32 csp_mipi_dlane_state(void *base);

u32 csp_mipi_clane_state(void *base);

/**
 * Config MIPI DPHY data ID
 */
u32 csp_mipi_dphy_data_id(void *base, u32 id, u32 dt, u32 vc);


/**
 * Read MIPI DPHY register
 */
u32 csp_mipi_dphy_read(u8 addr);

/**
 * Write MIPI DPHY register
 */
u32 csp_mipi_dphy_write(u8 addr, u8 wval);


/**
 * MIPI DPHY Init
 */
u32 csp_mipi_dphy_init(void *base, u32 lane, u32 id, u32 dt, u32 vc,
			u32 freq, u32 csi_id);

/**
 * csp_mcsi_dump_regs - dump all the register
 */
void csp_mcsi_dump_regs(const char *func_name);

/**
 * enable mcsi output raw msb data
 */
u32 csp_enable_mcsi_output_raw_msb_data(void *base);

/**
 * enable mcsi output high 8bit data
 */
u32 csp_enable_mcsi_output_high_8bit_data(void *base);


#endif /* ___VISS_MIPI__CSI___H___ */
